The present invention relates to a semiconductor integrated circuit technique. More particularly, it relates to an electrostatic discharge protection circuit applied to a semiconductor integrated circuit, which is triggered to conduct through PNP bipolar action.
In the processes of measuring, assembling, installing and using an integrated circuit, Electrostatic Discharge (ESD) is unavoidable and may cause damage to integrated circuits. At present, there are many models explaining the causes of ESD, wherein the human body model is most common. The human body model refers to the ESD pulse caused by a human body""s contact with the pins of an integrated circuit. Since the ESD pulse of the human body model lasts longest, the makers use this as a standard for integrated circuit ESD protection.
With the adoption of the Lightly Doped Drain (LDD) structure and the self-aligned mental salicide diffusion production process, the Lateral Semiconductor Controlled Rectifier has been applied as an ESD protection circuit in CMOS integrated circuits, as disclosed in U.S. Pat. No. 5,012,317. The Lateral Semiconductor Controlled Rectifier, disclosed in U.S. Pat. No. 5,012,317, is triggered by a P/N junction breakdown between the well region and the base. However, in practical applications, the trigger voltage is above 30V. For sub-micron or half-micron COMS devices, the gate oxide is damaged by this trigger voltage. Therefore, the Lateral Semiconductor Controlled Rectifier of the prior art doesn""t provide effective ESD protection.
To reduce the trigger voltage, U.S. Pat. No. 5,465,189 provides a semiconductor controlled rectifier triggered by a low voltage. It uses a device similar to NMOS to provide a thickly doped region across the junction between the well region and the base. When the ESD occurs, the junction breakdown of the thickly doped region of the device causes the semiconductor controlled rectifier to be triggered to conduct; thereby, the trigger voltage of the ESD protection circuit is reduced. However, if the diffusion production process of the self-aligned mental salicide is applied to the source or drain of the device, the effect of ESD protection will be reduced.
It is an object of the invention to provide an ESD protection circuit for semiconductor integrated circuits, which triggers the semiconductor controlled rectifier by using the PMOS device through PNP bipolar action. According to the invention, the ESD protection circuit offers the advantages of ESD protection and compatibility with the self-aligned mental salicide diffusion production process.
To achieve the above-mentioned object, the present invention provides an ESD protection circuit. The ESD protection circuit comprises a semiconductor controlled rectifier and a PMOS device. The semiconductor controlled rectifier coupled between two nodes has an N-type semiconductor layer. The PMOS device shares a first P-type doped region with the semiconductor controlled rectifier and comprises a PNP device located in the N-type semiconductor layer. When one of the nodes is coupled to the ESD power, the PNP device will conduct to trigger the semiconductor controlled rectifier.
Therefore, since the semiconductor controlled rectifier conduction is triggered to conduct through the PNP bipolar action, the ESD protection circuit has the advantages of ESD protection and compatibility with the self-aligned mental salicide diffusion production process.